Miniaturized on-chip passive devices for millimetre-wave applications in Bi-CMOS technology

University of Technology Sydney. Faculty of Engineering and Information Technology.Recent advances in silicon-based integrated circuits (ICs) have successfully demonstrated promising system-on-chip (SoC) solutions to support micro- and millimeter-wave (mm-wave) applications. As the end of Moore’s Law is approaching, the full potential of active devices is eventually going to be reached. The technical advancement of these emerging technologies can further push through the introduction of alternative equivalent scaling techniques such as the implementation of new design geometries. As the interest in the mm-wave band grows, circuit miniaturization is faced with a unique set of challenges and constraints. In this work, we looked at the growing potential of monolithic integration to design high-performance transceiver system building blocks. This thesis presents a passive inspired implementation of resonator and bandpass filters designed, and fabricated using IHP 0.13 μm SiGe Bi-CMOS process. Two unique miniaturization design methodologies are presented in this work. In order to fully demonstrate the insight of this approach, a simplified equivalent LC-circuit model is used for theoretical analysis. Using the analyzed results as a guideline along with a full-wave electromagnetic (EM) simulator, two compact bandpass filters (BPFs) are implemented and designed for mm-wave applications. The first design methodology is a folded-strip-line-based design. The proposed method is based on a planar structure in which neither broadside coupling nor crossover between metals is required. Only a single metal layer is used to implement a compact resonator. To demonstrate its flexibility a BPF is designed. The 1st BPF has one transmission zero at 58 GHz with a peak attenuation of 23 dB. The center frequency of this filter is 27 GHz with an insertion loss of 2.5 dB, while the S₁₁ is better than 10 dB from 26 to 31 GHz. The 2nd BPF has two transmission zeros, and a minimum insertion loss of 3.5 dB is found at 29 GHz. The S₁₁ is better than 10 dB from 26 GHz to 34 GHz. Also, more than 20 dB stop-band attenuation is achieved from DC to 20.5 GHz and from 48 GHz to 67 GHz. The chip sizes of these two BPFs, excluding the pads, are only 0.023 mm² and 0.028 mm², respectively. The second methodology is designed with ultra-wideband and low insertion loss. The proposed approach uses merely a combination of meander-line structures with metal-insulator-metal (MIM) capacitors. For the 1st BPF, the return loss is better than 10 dB from 13.5 to 32 GHz, which indicates a fractional bandwidth of more than 78%. Also, the minimum insertion loss of 2.3 dB is achieved within the frequency range from 17 GHz to 27 GHz, and the in-band magnitude ripple is less than 0.1 dB. The chip size of this design, excluding the pads, is 0.148 mm². To demonstrate a miniaturized design, a 2nd design example is given. The return loss is better than 10 dB from 17.3 to 35.9 GHz, which indicates a fractional bandwidth of more than 70%. Also, the minimum insertion loss of 2.6 dB is achieved within the frequency range from 21.4 GHz to 27.7 GHz, and the in-band magnitude ripple is less than 0.1 dB. The chip size of the 2nd design, excluding the pads, is only 0.066 mm². The overall performances of both proposed structures are suitable for miniaturizing design in silicon-based technology. The presented design can be useful to co-design with active devices. As compared to the previously published literature, the presented design in this thesis offer a promising solution in scaling down the physical size of the passive component

Compact Millimeter-Wave Bandpass Filters Using Quasi-Lumped Elements in 0.13-um (Bi)-CMOS Technology for 5G Wireless Systems

© 2019 IEEE.A design methodology for a compact millimeter-wave on-chip bandpass filter (BPF) is presented in this paper. Unlike the previously published works in the literature, the presented method is based on quasi-lumped elements, which consists of a resonator with enhanced self-coupling and metal-insulator-metal capacitors. Thus, this approach provides inherently compact designs comparing with the conventional distributed elements-based ones. To fully understand the insight of the approach, simplified LC-equivalent circuit models are developed. To further demonstrate the feasibility of using this approach in practice, the resonator and two compact BPFs are designed using the presented models. All three designs are fabricated in a standard 0.13- \mu \text{m} (Bi)-CMOS technology. The measured results show that the resonator can generate a notch at 47 GHz with the attenuation better than 28 dB due to the enhanced self-coupling. The chip size, excluding the pads, is only 0.096 \times 0.294 mm 2. In addition, using the resonator for BPF designs, the first BPF has one transmission zero at 58 GHz with a peak attenuation of 23 dB. The center frequency of this filter is 27 GHz with an insertion loss of 2.5 dB, while the return loss is better than 10 dB from 26 to 31 GHz. The second BPF has two transmission zeros, and a minimum insertion loss of 3.5 dB is found at 29 GHz, while the return loss is better than 10 dB from 26 GHz to 34 GHz. Also, more than 20-dB stopband attenuation is achieved from dc to 20.5 GHz and from 48 to 67 GHz. The chip sizes of these two BPFs, excluding the pads, are only 0.076\times 0.296 mm 2 and 0.096\times 0.296 mm 2, respectively.Peer reviewe

PaST-NoC: A Packet-Switched Superconducting Temporal NoC

Temporal computing promises to mitigate the stringent area constraints and clock distribution overheads of traditional superconducting digital computing. To design a scalable, area- and power-efficient superconducting network on chip (NoC), we propose packet-switched superconducting temporal NoC (PaST-NoC). PaST-NoC operates its control path in the temporal domain using race logic (RL), combined with bufferless deflection flow control to minimize area. Packets encode their destination using RL and carry a collection of data pulses that the receiver can interpret as pulse trains, RL, serialized binary, or other formats. We demonstrate how to scale up PaST-NoC to arbitrary topologies based on 2x2 routers and 4x4 butterflies as building blocks. As we show, if data pulses are interpreted using RL, PaST-NoC outperforms state-of-the-art superconducting binary NoCs in throughput per area by as much as 5x for long packets.Comment: 14 pages, 18 figures, 2 tables. In press in IEEE Transactions on Applied Superconductivit

Subthreshold energy harvesters circuits for biomedical implants applications

This paper reviews the state-of-art of the subthreshold level design energy harvesters for powering biomedical implants. Power consumption and lifespan are crucial requirements for the electronic circuitry of implantable systems. In order to meet these challenging requirements, a design for an energy harvester that operates in a subthreshold level offers a promising solution.5 page(s

Design of low power, high PSRR low drop-out voltage regulator

This paper presents a low power, low drop-out (LDO) voltage regulator, designed and implemented using 0.18 micron CMOS process. With a supply voltage of 1.8V, 50mA current and with a single compensation capacitor of 1pF. A constant transconductance current reference is used as a bias circuit for the Error Amplifier. The maximum output load current is 50mA at a regulated output voltage of 1.68V.The voltage regulator delivers a full load transient response of 5.5mV overshoot and 3.4mV undershoot. Furthermore, the LDO PSRR rating is -73dB @ 16.7MHz, and a relatively low power of 90mW.5 page(s